The present invention relates to testing of dynamic random access memories (DRAMs). More particularly, the present invention relates to performance measurements of key portions of a DRAM.
Historically, semiconductor chips used in electronic systems, including, but not limited to, computers and controllers, have been of two main types. A first type of chip is built with a process optimized for high-speed logic. The actual speed of xe2x80x9cHigh-speed logicxe2x80x9d has been constantly increasing for many years; at any point in time, high-speed logic is the logic used for leading-edge computer, controller, and Application Specific Integrated Circuit (ASIC) products. Currently, such high-speed logic is implemented in Complementary Metal Oxide Semiconductor (CMOS) semiconductor processes. Short Field Effect Transistor (FET) channel length and very thin gate oxide thickness, as well as low FET threshold voltage are typical characteristics of CMOS FETs that are optimized for very high speed. Process technology advances usually comprise improvements in some or all of these characteristics.
A second type of chip is built in a process optimized for dense data storage and length of data retention in dynamic random access memory (DRAM). A DRAM technology stores information by placing (or not placing) charge on a capacitor to write the information. Later, during a read operation, the presence (or absence) of charge on the capacitor is sensed. A requirement of such DRAM data storage is that the capacitor must retain the charge for a significant period of time. Eventually, DRAM capacitors lose charge through leakage mechanisms and must be periodically refreshed. During refresh periods, the data cannot be read. Therefore, higher memory availability (and higher system throughput) results from longer data retention by the DRAM capacitors. A DRAM storage cell, shown in FIG. 1, comprises a storage capacitor, a strap resistance, and a DRAM transistor. A drain of the DRAM transistor is coupled to a bitline; a gate of the DRAM transistor is coupled to a wordline.
The DRAM transistor is not required to provide ultrahigh speed; rather, it must be designed to keep leakage currents small, thereby extending retention time of charge placed through the DRAM transistor from the bitline into the storage capacitor. DRAM transistors typically have relatively high FET thresholds, compared to FET thresholds of FETs used in high-speed logic. DRAM transistors also typically have thicker gate oxides and longer channel lengths than FETs used in high-speed logic.
Read performance of the DRAM storage cell depends largely on the DRAM transistor, the value of the strap resistance, and the capacitance of the storage capacitor. If a xe2x80x9c0xe2x80x9d is written into the DRAM storage cell by discharging the storage capacitor, the xe2x80x9c0xe2x80x9d is read by charging the bitline to a xe2x80x9c1xe2x80x9d and then floating the bitline. Floating the bitline means removing active drive from the bitline. When floated, capacitance on the bitline maintains the bitline voltage at substantially the voltage to which the bitline was charged. Then, the wordline is activated, turning on the DRAM transistor. A charge redistribution occurs between the precharged bitline and the discharged (i.e., xe2x80x9c0xe2x80x9d) storage capacitor. The redistribution has to flow through the DRAM transistor and the strap resistance. A high strap resistance value and/or a slow DRAM transistor makes the DRAM storage cell read slower; a low strap resistance and/or a fast DRAM transistor makes the DRAM storage cell read faster. A storage capacitor with a larger capacitance value causes the bitline to fall further, in which case, voltage on the bitline will reach a switching threshold on a sense amplifier (to be shown and discussed later) in a shorter period of time. The value of the storage capacitor, the value of the strap resistance, and the characteristics of the DRAM transistor all are parameters that vary from chip to chip as semiconductor chips are processed in a semiconductor processing factory. Therefore, DRAM storage cells will be faster on some chips than on other chips.
In recent years, DRAM memory has been placed on high-speed logic chips. DRAM memory is much denser than static random access memory (SRAM). Although SRAM is typically used for level-1(L1) cache memory on high-speed logic chips such as processors, the density advantage of DRAM often justifies the use of DRAM, especially for embedded level-2 (L2) cache, where bandwidth and memory capacity are more important than latency. To achieve both high speed in the logic and long data retention time in the DRAM, such products typically use a process with short channel, low threshold voltage, thin gate oxide FETs for the high-speed logic. Such products also incorporate longer channel, higher threshold voltage, thicker gate oxide FETs for the DRAM transistors. Typically, special process steps are also used to produce relatively high capacitance DRAM storage capacitors. Even though a CMOS process capable of putting both types of FETs on the same chip is more complexxe2x80x94and therefore more expensivexe2x80x94performance improvements in the system, and possibly, savings in interface area costs from not having separate DRAM memory chips often justifies the use of embedded DRAM on high-speed logic chips.
A technique long used to characterize performance of circuits on semiconductor chips is to place a number of the circuits in a ring oscillator. Ring oscillators typically include a series of devices or stages connected together to form a ring with a feedback path provided from the output of the last of the series of devices to an input of the first device in the series of devices. The devices may include logic gates, inverters, differential buffers, or differential amplifiers, for example. Any inverting path with sufficient gain will oscillate when connected in a ring, while a non-inverting path will simply lock on a particular starting logic level. The ring oscillator is essentially a series of stages, each stage having an intrinsic delay from input to output. The frequency of the ring oscillator output is a function of the total delay time of the series of stages. Such ring oscillators have been common in ASICs and processors to determine the speed characteristics of a particular chip.
Devices of similar design track well across a semiconductor chip. That is, if a ring oscillator built out of inverters that are designed with high-speed logic performs xe2x80x9cfastxe2x80x9d, all logic circuits on a particular chip utilizing similar high-speed logic will also perform xe2x80x9cfastxe2x80x9d. Some variation may be expected and the variation can be quantified in any given process. Placement of several ring oscillators at different areas of a chip design allows the designer to account for xe2x80x9ccross-chipxe2x80x9d variations in performance. In very localized regions of a chip, parameters such as channel lengths track extremely well from one FET to another. Tracking of parameters between FETs at widely separated areas on a chip do not track as well as FETs that are very close. However, even FETs that are widely separated on a chip track better than chips processed on different wafers produced on different process lots, or even the same process lot.
Knowing the speed characteristics of a particular chip is valuable in order that the chip can be categorized as, for example, xe2x80x9cfastxe2x80x9d, xe2x80x9cnominalxe2x80x9d, or xe2x80x9cslowxe2x80x9d. Fast product can often be sold for a higher price than a nominal or slow product, thus making it important to know the speed characteristics. Such speed differentiation is sometimes known as xe2x80x9cspeed sortingxe2x80x9d, or xe2x80x9cbucketingxe2x80x9d.
When both high-speed logic circuits and embedded DRAM (EDRAM) exists on a single chip, both types of circuits must be characterized, since there is no significant tracking in characteristics between the dissimilar devices used in the high-speed logic circuits and the devices used in the DRAM storage cells. For example, even if the high-speed logic circuits are characterized as xe2x80x9cfastxe2x80x9d, the DRAM storage cells might be slow, and the chip could not be categorized as xe2x80x9cfastxe2x80x9d.
There are classes of circuits in which the measured performance of only one of the input transitions is desired. These classes of circuits include, for example, dynamic circuits, memory paths, and the like. Application Ser. No. 09/977,423 earlier included in its entirety, describes a method and ring oscillator suitable for evaluating dynamic circuits. Application Ser. No. 09/977,423 teaches measuring performance of circuits in which the measured performance of only one of the input transitions is desired; however, application Ser. No. 09/977,423 does not teach a circuit configuration or method for characterizing the performance of a DRAM storage cell.
Therefore, there is a need for a method and apparatus suitable for characterizing the performance of a DRAM storage cell.
In brief, a method and circuitry is disclose that provide for inclusion of a DRAM storage cell as a determinate portion of a ring oscillator""s frequency. The circuitry includes necessary timing and control elements that ensure that the DRAM storage cell is precharged when it needs to be precharged, reset when it needs to be reset, and read in a way that the delay of the DRAM storage cell can be determined. The present invention discloses a method and apparatus suitable for characterizing the performance of a DRAM storage cell.
In an embodiment, semiconductor chip comprises a DRAM storage cell placed in a ring oscillator that measures performance of the DRAM storage cell.
In an exemplary embodiment of the ring oscillator on this semiconductor chip, a determinant of the ring oscillator""s frequency is the time needed by the DRAM storage cell to discharge a bitline capacitance to a predetermined voltage.
In another exemplary embodiment of the ring oscillator on this semiconductor chip, a DRAM storage cell""s storage capacitor is discharged, and a bitline is charged. Subsequently, a word line is activated, causing charge redistribution to occur between the bitline and the storage capacitor, with current flowing through a DRAM transistor and a strap resistance.
In a further embodiment, the DRAM storage cell is bypassed in the ring oscillator, allowing computation of ring oscillator period difference between the period with the DRAM storage cell delay and without the DRAM storage cell delay.